Ontwerp van ingebedde STT-MRAM cellen vanaf de 10 nm finFET generatie

摘要

Memories which are embedded on the same physical chip as the processor, are becoming dominant in chip area as opposed to the processor itself. Spin-Transfer Torque Magnetic Random Access Memory or STT-MRAM is being proposed as an area efficient alternative to the common Static Random Access Memory or SRAM. In the technology nodes when STT-MRAM should be introduced, in and beyond the 10 nm node, the manufacturing process of semi-conductor chips has undergone some significant changes. The most important changes are the use of fixed size "fin"-based transistors and the use of multiple patterning techniques to allow the creation of small and dense physical structures. The manufacturing of the embedded memory and the design of the memory cells needs to be fully compatible with this process in all three dimensions in order to guarantee successful integration.A thorough analysis of the physical layout of embedded STT-MRAM cells in the 10 nm and 7 nm node shows the importance of secondary design rules impacted by the different multiple patterning techniques. Process techniques to enhance the size scaling such as multi-level via's can effectively reduce the size of STT-MRAM cells and are imperative for future scaling. Two novel cell designs targeting area density and high performance respectively, show the importance of making the link to the physical implementation. They are optimized to counter the ever increasing parasitic resistance of the interconnect lines and show how through inclusive design,more is actually less!