Oscillator Architectures and Enhanced Frequency Synthesizer

摘要

A voltage controlled oscillator (VCO), that generates a periodic signal whose frequency is tuned by a voltage, is a key building block in any integrated circuit systems.A sine wave oscillator can be used for a built-in self testing where high linearity isrequired. A bandpass filter (BPF) based oscillator is a preferred solution, and highquality factor (Q-factor) is needed to improve the linearity. However, a stringentlinearity specification may require very high Q-factor, not practical to implement. Toaddress this problem, a frequency harmonic shaping technique is proposed. It utilizes afinite impulse response filter improving the linearity by rejecting certain harmonics. Aprototype SC BPF oscillator with an oscillating frequency of 10 MHz is designed andmeasurement results show that linearity is improved by 20 dB over a conventionaloscillator.In radio frequency area, preferred oscillator structures are an LC oscillator and aring oscillator. An LC oscillator exhibits good phase noise but an expensive cost of aninductor is disadvantageous. A ring oscillator can be built in standard CMOS process,but suffers due to a poor phase noise and is sensitive to supply noise. A RC BPFoscillator is proposed to compromise the above difficulties. A RC BPF oscillator at 2.5GHz is designed and measured performance is better than ring oscillators whencompared using a figure of merit. In particular, the frequency tuning range of theproposed oscillator is superior to the ring oscillator.VCO is normally incorporated with a frequency synthesizer (FS) for an accuratefrequency control. In an integer-N FS, reference spur is one of the design concerns incommunication systems since it degrades a signal to noise ratio. Reference spurs can berejected more by either the lower loop bandwidth or the higher loop filter. But theformer increases a settling time and the latter decreases phase margin. An adaptivelowpass filtering technique is proposed. The loop filter order is adaptively increasedafter the loop is locked. A 5.8 GHz integer-N FS is designed and measurement resultsshow that reference spur rejection is improved by 20 dB over a conventional FS withoutdegrading the settling time. A new pulse interleaving technique is proposed and severaldesign modifications are suggested as a future work.