This thesis presents a low-power LDPC decoder design based on speculative scheduling of energy necessary to decode dynamically varying data frame in both block-fadingchannels and general AWGN channels. A model of a memory-efficient low-powerhigh-throughput multi-rate array LDPC decoder as well as its FPGA implementa-tion results is first presented. Then, I propose a decoding scheme that provides thefeature of constant-time decoding and thus facilitates real-time applications whereguaranteed data rate is required. It pre-analyzes each received data frame to estimate the maximum number of necessary iterations for frame convergence. Theresults are then used to dynamically adjust decoder frequency and switch betweenmultiple-voltage levels; thereby energy use is minimized. This is in contrast to theconventional fixed-iteration decoding schemes that operate at a fixed voltage levelregardless of the quality of data received. Analysis shows that the proposed decodingscheme is widely applicable for both two-phase message-passing (TPMP) decodingalgorithm and turbo decoding message passing (TDMP) decoding algorithm in blockfading channels, and it is independent of the specific LDPC decoder architecture. Adecoder architecture utilizing our recently published multi-rate decoding architecturefor general AWGN channels is also presented. The result of this thesis is a decoderdesign scheme that provides a judicious trade-off between power consumption andcoding gain.
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