Higher data rate hard disk drives(HDD) and improved read channel electronics are demanding preamplifier performance be extended well beyond 1 Gb/s. Historically, preamplifier power requirements were of low priority; however, with increased demand for battery powered devices such as laptops, MP3 players, personal video recorders, andmanyother wireless hand-held devices, power consumption has become an important design parameter.Furthermore, in order to continue to increase drive capacities, new read-write head technologies(vertical recording and TGMR heads) are demanding innovative preamplifier circuitsolutions.Today's production preamplifiers possess a wide band response of 2.5 MHz-600 MHz; however next generation preamplifiers willrequire response greater than 250 KHz-1 GHz.Low corner frequencies below 250 KHz present read recovery (sleep-to-read, write-to-read, etc) challenges which can limit drive capacity. This project targets a > 2 Gb/s TGMR (tunneling giantmagneto-resistive) read path for verticalrecording HDDs. A high performance BiCMOS process (IBM's 0.5?m 5HP process)is essential due to the large transconductances, low noise and highspeed requirements of the read path's first stage. System frequency limitations at the input are a result of the large TGMR read sensor and preamplifier input capacitance. Due to read head and preamplifier manufacturingvariations, resistive feedbackaroundthe firststage is usedto seta controlled input impedance targeted to match the interconnect transmission line. Head resistance variations lead to gain variations; however, the TGMR element becomes more sensitive with larger resistance. This, to a first order approximation, acts like an automatic gain control and reduces variations in gain due to the head.
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