Increasing relative semiconductor process variations are making the prediction ofrealistic worst-case integrated circuit delay or sign-off yield more difficult. As processgeometries shrink, intra-die variations have become dominant and it is imperative tomodel them to obtain accurate timing analysis results. In addition, intra-die processvariations are spatially correlated due to pattern dependencies in the manufacturingprocess. Any statistical static timing analysis (SSTA) tool is incomplete without a modelfor signal crosstalk, as critical path delays can increase or decrease depending on theswitching of capacitively coupled nets. The coupled signal timing in turn depends on theprocess variations. This work describes an SSTA tool that models signal crosstalk andspatial correlation in intra-die process variations, along with gradients and inter-dievariations.
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