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AN OPTIMISED SYSTOLIC ARRAY-BASED MATRIX INVERSION FOR RAPID PROTOTYPING OF KALMAN FILTERS IN FPGA’S

机译：FPGA中卡尔曼滤波器快速原型的基于最优矩阵的基于矩阵的矩阵求逆

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Lai Yat Tin; Bigdeli Abbas; Biglari-Abhari Morteza;
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年度 2004
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1. A New Pipelined Systolic Array-Based Architecture for Matrix Inversion in FPGAs with Kalman Filter Case Study [J] . Abbas Bigdeli, Morteza Biglari-Abhari, Zoran Salcic, EURASIP journal on applied signal processing . 2006,第14期

机译：基于卡尔曼滤波器的FPGA中基于矩阵矩阵的流水线脉动阵列新架构案例研究
2. A New Pipelined Systolic Array-Based Architecture for Matrix Inversion in FPGAs with Kalman Filter Case Study [J] . Abbas Bigdeli, Morteza Biglari-Abhari, Zoran Salcic, EURASIP journal on advances in signal processing . 2006,第1期

机译：基于卡尔曼滤波器的FPGA中基于矩阵矩阵的流水线脉动阵列新架构案例研究
3. A Methodology for Rapid Prototyping Peak-Constrained Least-Squares Bit-Serial Finite Impulse Response Filters in FPGAs [J] . Alex Carreira, Trevor W. Fox, Laurence E. Turner EURASIP journal on advances in signal processing . 2003,第6期

机译：在FPGA中快速原型化峰值约束最小二乘位串行有限冲激响应滤波器的方法
4. AN OPTIMISED SYSTOLIC ARRAY-BASED MATRIX INVERSION FOR RAPID PROTOTYPING OF KALMAN FILTERS IN FPGA'S [C] . Yat Tin Lai, Abbas Bigdeli, Morteza Biglari-Abhari European Signal Processing Conference(EUSIPCO 2004) vol.3; 20040906-10; Vienna(AT) . 2004

机译：FPGA中卡尔曼滤波器快速原型的基于优化矩阵的基于矩阵的矩阵求逆
5. FPGA design and implementation of systolic array-based Viterbi decoders. [D] . Guo, Man. 2002

机译：基于脉动阵列的Viterbi解码器的FPGA设计和实现。
6. A Systolic Array-Based FPGA Parallel Architecture for the BLAST Algorithm [O] . Xinyu Guo, Hong Wang, Vijay Devabhaktuni 2012

机译：用于BLAST算法的基于脉动阵列的FPGA并行架构
7. A New Pipelined Systolic Array-Based Architecture for Matrix Inversion in FPGAs with Kalman Filter Case Study [O] . Abbas Bigdeli, Morteza Biglari-Abhari, Zoran Salcic, 2006

机译：基于卡尔曼滤波器的FPGA中基于矩阵矩阵的流水线脉动阵列新架构案例研究
8. Systolic VLSI for Kalman filters [R] . Yeh, H.-G., Chang, J. J. 1986

机译：卡尔曼滤波器的收缩VLsI

AN OPTIMISED SYSTOLIC ARRAY-BASED MATRIX INVERSION FOR RAPID PROTOTYPING OF KALMAN FILTERS IN FPGA’S

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