Due to increased variation in modern process technology nodes, the spatial correlation of variation is a key issue for both modeling and design. We have created a large array test-structure to analyze the magnitude of spatial correlation of threshold voltage (VT) in a 180 nm CMOS process. The data from over 50 k measured devices per die indicates that there is no significant within-die spatial correlation in VT. Furthermore, the across-chip variation patterns between different die also do not correlate. This indicates that Random Dopant Fluctuation (RDF) is the primary mechanism responsible for VT variation and that relatively simple Monte Carlo-type analysis can capture the effects of such variation. While high performance digital logic circuits, at high VDD , can be strongly affected by spatially correlated channel length variation, we note that subthreshold logic will be primarily affected by random uncorrelated VT variation.
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