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Performance investigation of asymmetric double‐gate doping less tunnel FET with Si/Ge heterojunction

机译：具有SI / GE异质结的非对称双栅掺杂的性能调查较少的隧道FET

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Suruchi Sharma; Baljit Kaur;
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1. Performance investigation of asymmetric double-gate doping less tunnel FET with Si/Ge heterojunction [J] . Sharma Suruchi, Kaur Baljit Circuits, Devices & Systems, IET . 2020,第5期

机译：具有SI / GE异质结的非对称双栅掺杂的性能调查较少的隧道FET
2. Investigation of geometrical and doping parameter variations on GaSb/Si‐based double gate tunnel FETs: A qualitative and quantitative approach for RF performance enhancement [J] . Shanmuganathan Poorvasha, Balasubramanian Lakshmi International journal of numerical modelling . 2019,第6期

机译：基于GaSb / Si的双栅极隧道FET的几何和掺杂参数变化研究：提高RF性能的定性和定量方法
3. Capacitorless one-transistor dynamic random-access memory based on asymmetric double-gate Ge/GaAs-heterojunction tunneling field-effect transistor with n-doped boosting layer and drain-underlap structure [J] . Yoon Young Jun, Seo Jae Hwa, Kang In Man Japanese journal of applied physics . 2018,第4S期

机译：基于非对称双栅Ge / GaAs-异质结隧穿场效应晶体管的无电容器单晶体管动态随机存取存储器，具有n掺杂的升压层和漏极-下覆结构
4. Performance Investigation of a Si/Ge Heterojunction Asymmetric Double Gate DLTFET Considering Temperature and ITC Variations [C] . Suruchi Sharma, Rikmantra Basu, Baljit Kaur International Symposium on Quality Electronic Design . 2021

机译：考虑温度和ITC变化的SI / GE异质结不对称双栅DLTFET的性能研究
5. Development of a process flow for self -aligned double -gate MOSFET by tunnel epitaxy using nitrided thermal oxide as gate insulators. [D] . Ahmed, Shibly Sadique. 2001

机译：通过隧道外延，使用氮化的热氧化物作为栅绝缘体，开发自对准双栅MOSFET的工艺流程。
6. Design of High Performance Si/SiGe Heterojunction Tunneling FETs with a T-Shaped Gate [O] . Wei Li, Hongxia Liu, Shulong Wang, 2017

机译：具有T形栅极的高性能Si / SiGe异质结隧穿FET的设计
7. A SiGe-Source Doping-Less Double-Gate Tunnel FET: Design and Analysis Based on Charge Plasma Technique with Enhanced Performance [O] . Varun Mishra, Yogesh Kumar Verma, Santosh Kumar Gupta, 2021

机译：一种SiGe源掺杂的双栅极隧道FET：基于增强性能的充电等离子体技术的设计与分析

Performance investigation of asymmetric double‐gate doping less tunnel FET with Si/Ge heterojunction

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