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Single-Grain Gate-All-Around Si Nanowire FET Using Low-Thermal-Budget Processes for Monolithic Three-Dimensional Integrated Circuits

机译：单粒门 - 全围绕单片三维集成电路的低热预算过程的Si纳米线FET

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Tung-Ying Hsieh; Ping-Yi Hsieh; Chih-Chao Yang; Chang-Hong Shen; Jia-Min Shieh; Wen-Kuan Yeh; Meng-Chyi Wu;
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1. Three-dimensional monolithic microwave integrated circuit technology for fully computer-aided design-compatible monolithic microwave integrated circuit development [J] . Kenjiro Nishikawa, Ichihiko Toyoda, Kenji Kamogawa, International journal of RF and microwave computer-aided engineering . 1998,第6期

机译：用于完全计算机辅助设计兼容的单片微波集成电路开发的三维单片微波集成电路技术
2. Negative differential conductivity and carrier heating in gate-all-around Si nanowire FETs and its impact on CMOS logic circuits [J] . Kaushik Nayak, Mohit Bajaj, Aniruddha Konar, Japanese journal of applied physics . 2014,第4S期

机译：全方位栅Si纳米线FET中的负差分电导率和载流子发热及其对CMOS逻辑电路的影响
3. High-Performance Poly-Si TFTs Using Ultrathin Gate Dielectric for Monolithic Three-Dimensional Integrated Circuits and System on Glass Applications [J] . Lee M. H., Wu S. L., Yang M.-J., Electron Device Letters, IEEE . 2010,第8期

机译：使用超薄栅极电介质的高性能多晶硅TFT用于单片三维集成电路和玻璃应用系统
4. Monolithic three-dimensional integrated circuits using carbon nanotube FETs and interconnects [C] . Hai Wei, Patil N., Lin A., Electron Devices Meeting (IEDM), 2009 . 2009

机译：使用碳纳米管FET和互连的单片三维集成电路
5. Characterization of vertical interconnects in three-dimensional monolithic microwave integrated circuits (three-dimensional MMIC). [D] . Kang, Qinghua (George). 2003

机译：三维单片微波集成电路（三维MMIC）中垂直互连的特性。
6. Single-Grain Gate-All-Around Si Nanowire FET Using Low-Thermal-Budget Processes for Monolithic Three-Dimensional Integrated Circuits [O] . Tung-Ying Hsieh, Ping-Yi Hsieh, Chih-Chao Yang, 2020

机译：单粒门 - 全围绕单片三维集成电路的低热预算过程的Si纳米线FET
7. Vertically integrated, three-dimensional nanowire complementary metal-oxide-semiconductor circuits [O] . Nam, SungWoo, Jiang, Xiaocheng, Xiong, Qihua, 2009

机译：垂直集成的三维纳米线互补金属氧化物半导体电路

Single-Grain Gate-All-Around Si Nanowire FET Using Low-Thermal-Budget Processes for Monolithic Three-Dimensional Integrated Circuits

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