首页> 外文OA文献 >PLI-TDC: Super Fine Delay-Time Based Physical-Layer Identification with Time-to-Digital Converter for In-Vehicle Networks

【2h】

PLI-TDC: Super Fine Delay-Time Based Physical-Layer Identification with Time-to-Digital Converter for In-Vehicle Networks

机译：PLI-TDC：基于超细延迟时间的物理层识别，具有车载网络的时间 - 数字转换器

代理获取

本网站仅为用户提供外文OA文献查询和代理获取服务，本网站没有原文。下单后我们将采用程序或人工为您竭诚获取高质量的原文，但由于OA文献来源多样且变更频繁，仍可能出现获取不到、文献不完整或与标题不符等情况，如果获取不到我们将提供退款服务。请知悉。

页面导航

著录项
引文网络
相似文献
相关主题

著录项

作者
Shuji Ohira; Araya Kibrom Desta; Ismail Arai; Kazutoshi Fujikawa;
展开▼
作者单位

展开▼
年度 2021
总页数
原文格式 PDF
正文语种
中图分类

相似文献

外文文献
中文文献
专利

1. An src="/images/tex/29719.gif" alt="80times "> Analog-Implemented Time-Difference Amplifier for Delay-Line-Based Coarse-Fine Time-to-Digital Converters in 0.18- src="/images/tex/21769.gif" alt="mu "> m CMOS [J] . Shih Horng-Yuan, Lin Sheng-Kai, Liao Po-Shun Very Large Scale Integration (VLSI) Systems, IEEE Transactions on . 2015,第8期

机译： src =“ / images / tex / 29719.gif” alt =“ 80times”> 基于延迟线的粗略精细时间的模拟实现时差放大器0.18- src =“ / images / tex / 21769.gif” alt =“ mu”> m CMOS的数字转换器
2. A High-Linearity, 17 ps Precision Time-to-Digital Converter Based on a Single-Stage Vernier Delay Loop Fine Interpolation [J] . Markovic B., Tisa S., Villa F. A., Circuits and Systems I: Regular Papers, IEEE Transactions on . 2013,第3期

机译：基于单级游标延迟环精细插值的高线性度，17 ps精密时间数字转换器
3. Experimental Study of Machine-Learning-Based Detection and Identification of Physical-Layer Attacks in Optical Networks [J] . Carlos Natalino, Marco Schiano, Andrea Di Giglio, Journal of Lightwave Technology . 2019,第16期

机译：基于机器学习的光网络物理层攻击检测与识别实验研究
4. A robust and low-power synchronization technique of coarse-and-fine conversion parts in ring-oscillator-based time-to-digital converters [C] . Takayuki Okazawa, Ippei Akita IEEE International Conference on Electronics, Circuits and Systems . 2017

机译：基于环形振荡器的时间数字转换器中粗转换和精细转换部件的鲁棒且低功耗同步技术
5. A 0.1 PS Resolution Coarse-Fine Time-to-Digital Converter with 2.21 PS Single-Shot Precision [D] . Huang, Huihua. 2018

机译：具有2.21 PS单射精度的0.1 PS分辨率粗细的时间到数字转换器
6. A 13-Bit 12-ps Resolution Vernier Time-to-Digital Converter Based on Dual Delay-Rings for SPAD Image Sensor [O] . Zunkai Huang, Jinglin Huang, Li Tian, 2021

机译：基于双延迟环的33位12-PS分辨率的乘法时间转换器用于SPAD图像传感器
7. A Phased-Scaled Vernier Time-to-Digital Converter Architecture with Switchable Coarse/Fine Resolutions, Wide Range and Ultra Low Power Consumption [O] . Tuoxin Wang -1

机译：具有可切换粗/精细分辨率的相位缩放的游标时间到数字转换器架构，宽范围和超低功耗

PLI-TDC: Super Fine Delay-Time Based Physical-Layer Identification with Time-to-Digital Converter for In-Vehicle Networks

著录项

引文网络

相似文献

相关主题

期刊订阅