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Towards IP integration on SoC: a case study of high‐throughput and low‐cost wrapper design on a novel IBUS architecture

机译：对SOC的知识产权集成：采用新型IBUS架构的高通量和低成本包装设计的案例研究

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Xiaokun Yang; Shi Sha; Ishaq Unwala; Jiang Lu;
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1. Towards IP integration on SoC: a case study of high-throughput and low-cost wrapper design on a novel IBUS architecture [J] . Yang Xiaokun, Sha Shi, Unwala Ishaq, Computers & Digital Techniques, IET . 2020,第6期

机译：对SOC的知识产权集成：采用新型IBUS架构的高通量和低成本包装设计的案例研究
2. Design of low-cost and high-throughput linear arrays for DFT computations: algorithms, architectures, and implementations [J] . Shen-Fu Hsiao, Wei-Ren Shiue IEEE Transactions on Circuits and Systems. II, Express Briefs . 2000,第11期

机译：用于DFT计算的低成本，高吞吐量线性阵列的设计：算法，体系结构和实现
3. Design of low-cost and high-throughput linear arrays for DFT computations: algorithms, architectures, and implementations [J] . Shen-Fu Hsiao, Wei-Ren Shiue IEEE Transactions on Circuits and Systems. II . 2000,第11期

机译：用于DFT计算的低成本，高吞吐量线性阵列的设计：算法，体系结构和实现
4. Unifying memory and processor wrapper architecture in multiprocessor SoC design [C] . Ferid Gharsalli, Damien Lyonnard, Samy Meftali, International symposium on System Synthesis . 2002

机译：在多处理器SoC设计中统一内存和处理器包装器体系结构
5. Implementation of Low Cost, High-Throughput and High Sensitive Biomarker Detection Technique in Serum/Plasma Samples by Integrating Dielectrophoresis and Fluorescence Based Platform [D] . Logeeshan, Velmanickam 2019

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7. Unifying memory and processor wrapper architecture in multiprocessor SoC design [O] . Gharsalli, F., Lyonnard, D., Meftali, A., 2002

机译：在多处理器SoC设计中统一内存和处理器包装器体系结构
8. Design and Development of an Equipotential Voltage Reference (Grounding) System for a Low-Cost Rapid-Development Modular Spacecraft Architecture [R] . Lukash, J. A., Daley, E. 2011

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Towards IP integration on SoC: a case study of high‐throughput and low‐cost wrapper design on a novel IBUS architecture

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