Energy-Efficient Time-Domain Vector-by-Matrix Multiplier for Neurocomputing and Beyond

摘要

We propose an extremely energy-efficient mixed-signal approach for performingvector-by-matrix multiplication in a time domain. In such implementation,multi-bit values of the input and output vector elements are represented withtime-encoded digital signals, while multi-bit matrix weights are realized withcurrent sources, e.g. transistors biased in subthreshold regime. With ourapproach, multipliers can be chained together to implement large-scale circuitscompletely in a time domain. Multiplier operation does not rely onenergy-taxing static currents, which are typical for peripheral andinput/output conversion circuits of the conventional mixed-signalimplementations. As a case study, we have designed a multilayer perceptron,based on two layers of 10x10 four-quadrant vector-by-matrix multipliers, in55-nm process with embedded NOR flash memory technology, which allows forcompact implementation of adjustable current sources. Our analysis, based onmemory cell measurements, shows that at high computing speed the drain-inducedbarrier lowering is a major factor limiting multiplier precision to ~6 bit.Post-layout estimates for a conservative 6-bit digital input/output NxNmultiplier designed in 55 nm process, including I/O circuitry for convertingbetween digital and time domain representations, show ~7 fJ/Op for N>200, whichcan be further lowered well below 1 fJ/Op for more optimal and aggressivedesign.