首页> 外文OA文献 >Efficient Approach for Electrical Design and Analysis of High-Speed Interconnect in Integrated Circuit Packages
【2h】

Efficient Approach for Electrical Design and Analysis of High-Speed Interconnect in Integrated Circuit Packages

机译:集成电路封装中高速互连电气设计和分析的高效方法

代理获取
本网站仅为用户提供外文OA文献查询和代理获取服务,本网站没有原文。下单后我们将采用程序或人工为您竭诚获取高质量的原文,但由于OA文献来源多样且变更频繁,仍可能出现获取不到、文献不完整或与标题不符等情况,如果获取不到我们将提供退款服务。请知悉。

摘要

In recent integrated circuit (IC) packages, the structure of the interconnect is highly complex, and the effect of high-frequency parasitics is significant. These factors increase the number and level of design variables and extend the analysis frequency range to tens of gigahertz. As a result of the high dimensions of the design space, it is difficult to reduce the design gap between the current design approach and the physical limits of the practical IC-package interconnect. In this paper, we present an efficient approach for designing and analyzing the electrical characteristics of the high-speed interconnect in IC packages. The proposed approach is developed using a hybrid method involving the design of experiments, the domain decomposition method, and the finite-element method. We present a procedure to identify critical design variables for the IC-package interconnect, and we derive a method to recombine the impedance parameters of a segmented interconnect. The proposed hybrid method is verified by comparing its characteristic impedance (Zo) with the Zo value from a full-wave simulation of a complete interconnect. We demonstrate that the proposed hybrid method significantly reduces the design space of the IC-package interconnect so that we can efficiently and rapidly obtain the optimized solution, thereby improving the system performance.
机译:在最近的集成电路(IC)封装中,互连的结构是高度复杂的,并且高频寄生酶的效果是显着的。这些因素增加了设计变量的数量和水平,并将分析频率范围扩展到数十的Gigahertz。由于设计空间的高尺寸,难以降低当前设计方法与实用IC包互连的物理限制之间的设计间隙。在本文中,我们提出了一种设计和分析IC封装中高速互连电特性的有效方法。采用涉及实验设计的混合方法,域分解方法和有限元方法开发了所提出的方法。我们介绍了一种识别IC包互连的关键设计变量的过程,我们推导了一种重新组合分段互连的阻抗参数的方法。通过将其特征阻抗(ZO)与从完整互连的全波模拟进行比较,通过将其特征阻抗(ZO)与ZO值进行比较来验证所提出的混合方法。我们证明所提出的混合方法显着降低了IC-Packet互连的设计空间,使得我们可以有效且快速地获得优化的解决方案,从而提高了系统性能。

著录项

  • 作者

    Myunghoi Kim; Sunkyu Kong;

  • 作者单位
  • 年度 2020
  • 总页数
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类

相似文献

  • 外文文献
  • 中文文献
  • 专利
代理获取

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号