首页> 外文OA文献 >A VLSI Architecture for Output Probability Computations of HMM-Based Recognition Systems with Store-Based Block Parallel Processing

【2h】

A VLSI Architecture for Output Probability Computations of HMM-Based Recognition Systems with Store-Based Block Parallel Processing

机译：一种基于存储基于存储的块的识别系统的输出概率计算的VLSI体系结构

代理获取

本网站仅为用户提供外文OA文献查询和代理获取服务，本网站没有原文。下单后我们将采用程序或人工为您竭诚获取高质量的原文，但由于OA文献来源多样且变更频繁，仍可能出现获取不到、文献不完整或与标题不符等情况，如果获取不到我们将提供退款服务。请知悉。

页面导航

著录项
相似文献
相关主题

著录项

作者
Kazuhiro NAKAMURA; Masatoshi YAMAMOTO; Kazuyoshi TAKAGI; Naofumi TAKAGI;
展开▼
作者单位

展开▼
年度 2010
总页数
原文格式 PDF
正文语种
中图分类

相似文献

外文文献
中文文献
专利

1. A VLSI Architecture for Output Probability Computations of HMM-Based Recognition Systems with Store-Based Block Parallel Processing [J] . Kazuhiro NAKAMURA, Masatoshi YAMAMOTO, Kazuyoshi TAKAGI, IEICE transactions on information and systems . 2010,第2期

机译：基于HMM的识别系统基于存储的块并行处理的输出概率计算的VLSI架构
2. A VLSI Architecture for Output Probability Computations of HMM-Based Recognition Systems with Store-Based Block Parallel Processing [J] . Kazuhiro NAKAMURA, Masatoshi YAMAMOTO, Kazuyoshi TAKAGI, IEICE Transactions on Information and Systems . 2010,第2期

机译：基于HMM的识别系统基于商店的块并行处理的输出概率计算的VLSI架构
3. A Fast VLSI Architecture of Output Probability Computations and Viterbi Scorer for HMM-Based Recognition Systems with Store-Based Block Parallel Processing [J] . RYO SHIMAZAKI, KAZUHIRO NAKAMURA, MASATOSHI YAMAMOTO, 電子情報通信学会技術研究報告. コンピュ-タシステム. Computer Systems . 2009,第474期

机译：具有基于存储的块并行处理的基于HMM的识别系统的输出概率计算和维特比记分器的快速VLSI架构
4. Fast and Memory Efficient VLSI Architecture for Output Probability Computations of HMM-based Recognition Systems [C] . Kazuhiro Nakamura, Masatoshi Yamamoto, Kazuyoshi Takagi, International Symposium on Circuits and Systems . 2008

机译：基于HMM的识别系统的输出概率计算的快速和记忆高效的VLSI架构
5. Scalable parallel VLSI architectures and algorithms for digital signal and video processing. [D] . Elnaggar, Ayman Ibrahim. 1998

机译：用于数字信号和视频处理的可扩展并行VLSI架构和算法。
6. Probability-based nonlinear modeling of neural dynamical systems with point-process inputs and outputs [O] . Roman Sandler, Dong Song, Robert E Hampson, 2014

机译：具有点过程输入和输出的神经动力学系统的基于概率的非线性建模
7. Low Power VLSI Architecture of Viterbi Scorer for HMM-based Isolated Word Recognition [O] . Bok-gue Park, Koon-shik Cho, Jun-dong Cho 2012

机译：维特比记分器的低功耗VLSI架构，用于基于HMM的隔离词识别
8. Distributed Computing for Signal Processing: Modeling of Asynchronous Parallel Computation. Appendix C. Fault Tolerant Interconnection Networks and Image Processing Applications for the PASM Parallel Processing Systems [R] . Adams, G. B. 1984

机译：信号处理的分布式计算：异步并行计算的建模。附录C. pasm并行处理系统的容错互连网络和图像处理应用

A VLSI Architecture for Output Probability Computations of HMM-Based Recognition Systems with Store-Based Block Parallel Processing

著录项

相似文献

相关主题

期刊订阅