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A Low Impact Ionization Rate Poly-Si TFT with a Current and Electric Field Split Design

机译:具有电流和电场分流设计的低碰撞电离速率Poly-Si TFT

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摘要

In this study, a novel low impact ionization rate (low-IIR) poly-Si thin film transistor featuring a current and electric field split (CES) structure with bottom field plate (BFP) and partial thicker channel raised source/drain (RSD) designs is proposed and demonstrated. The bottom field plate design can allure the electron and alter the electron current path to evade the high electric field area and therefore reduce the device IIR and suppress the kink effect. A two-dimensional device simulator was applied to describe and compare the current path, electric field magnitude distributions, and IIR of the proposed structure and conventional devices. In addition, the advantages of a partial thicker channel RSD design are present, and the leakage current of CES-thin-film transistor (TFT) can be reduced and the ON/OFF current ratio be improved, owing to a smaller drain electric field.
机译:在本研究中,一种新的低碰撞电离速率(低IIR)多Si薄膜晶体管,具有底部场板(BFP)和部分较厚通道升降源/漏极(RSD)的电流和电场分割(CES)结构建议和展示设计。底部磁场板设计可以诱使电子和改变电子电流路径以避开高电场区域,从而减少装置IIR并抑制扭结效果。应用二维器件模拟器来描述和比较所提出的结构和传统设备的电流路径,电场幅度分布和IIR。另外,存在部分较厚的通道RSD设计的优点,并且由于较小的漏极电场,可以减小CES薄膜晶体管(TFT)的漏电流并改善开/关电流比。

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