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An Efficient High-Rate Non-Binary LDPC Decoder Architecture With Early Termination

机译:具有早期终止的高效高速非二元LDPC解码器架构

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摘要

This paper presents a modified Trellis Min-Max (T-MM) algorithm together with the associated architecture for non-binary (NB) low-density parity-check (LDPC) decoders. The proposed T-MM algorithm is able to reduce the memory requirements for the check-node messages through an efficient compression method and enhance the error-rate performance using the appropriate decompression. A method of updating the a posteriori log-likelihood ratio in the delta domain is used to simplify the computational and storage complexity. In order to enhance the decoding throughput, a low-complexity early termination (ET) scheme is devised by using the hard decisions of the variable-to-check messages, where, although a minor overhead is introduced, there is no visible degradation in error rate. As a proof of concept, a row-parallel layered decoder for the 32-ary (837, 726) LDPC code is implemented using a 90-nm CMOS process. The proposed decoder achieves a throughput of 1.64 Gb/s at 526.32 MHz based on eight iterations and has an area of 6.86 mm2. When the ET scheme is enabled, the decoder achieves a maximum throughput of 4.68 Gb/s with a frame error rate of 3.25 x 10^-6 at E_b/N_0 = 4.5 dB. The proposed NB-LDPC decoder achieves the highest throughput and hardware efficiency compared to the state-of-the-art decoders, even when the ET scheme is not enabled.
机译:本文介绍了改进的网格MIN-MAX(T-MM)算法以及相关的非二进制(NB)低密度奇偶校验(LDPC)解码器的相关架构。所提出的T-MM算法能够通过有效的压缩方法降低检查节点消息的存储器要求,并使用适当的解压缩来增强差错率性能。更新Delta域中的后验记录似然比的方法用于简化计算和存储复杂度。为了增强解码吞吐量,通过使用可变到检查消息的艰难决定,设计了低复杂性早期终止(et)方案,其中,虽然介绍了次要开销,但误差没有可见的降级速度。作为概念证据,使用90nm CMOS过程实现32-ary(837,726)LDPC代码的行并行分层解码器。该拟议的解码器基于8个迭代的526.32MHz实现1.64 GB / s的吞吐量,面积为6.86mm2。启用ET方案时,解码器可实现4.68 GB / s的最大吞吐量,帧误差率为3.25 x 10 ^ -6,在e_b / n_0 = 4.5 dB。对于未启用ET方案,所提出的NB-LDPC解码器与最先进的解码器相比,实现了最高的吞吐量和硬件效率。

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