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A simulation study of the influence of a high-k insulator and source stack on the performance of a double-gate tunnel FET

机译：高k绝缘子和源堆对双栅极隧道FET性能影响的仿真研究

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Mohammad Karbalaei; Daryoosh Dideban; Hadi Heidari;
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1. A simulation study of the influence of a high-k insulator and source stack on the performance of a double-gate tunnel FET [J] . Mohammad Karbalaei, Daryoosh Dideban, Hadi Heidari Journal of Computational Electronics . 2020,第3期

机译：高k绝缘子和源堆对双栅极隧道FET性能影响的仿真研究
2. Surface Potential Modeling of Graded-Channel Gate-Stack (GCGS) High-K Dielectric Dual-Material Double-Gate (DMDG) MOSFET and Analog/RF Performance Study [J] . Narendar Vadthiya, Girdhardas Kalola Ankit Silicon . 2018,第6期

机译：分级通道栅极堆叠的表面电位建模（GCG）高k电介质双材料双栅极（DMDG）MOSFET和模拟/射频性能研究
3. Double-Gate Negative-Capacitance MOSFET With PZT Gate-Stack on Ultra Thin Body SOI: An Experimentally Calibrated Simulation Study of Device Performance [J] . Ali Saeidi, Farzan Jazaeri, Igor Stolichnov, Electron Devices, IEEE Transactions on . 2016,第12期

机译：超薄体SOI上具有PZT栅极叠层的双栅极负电容MOSFET：器件性能的实验校准仿真研究
4. Performance Scrutiny of Source and Drain-Engineered Dual-Material Double-Gate (DMDG) SOI MOSFET with Various High-K [C] . Himanshu Yadav, R. K. Chauhan International Conference on Frontiers of Intelligent Computing : Theory and Applications . 2018

机译：具有各种高k的源极和漏油工程双层双门（DMDG）SOI MOSFET的性能审查
5. Planar source pocket (PSP) tunnel MOSFET: Potential device solution for low power applications and improving tunneling MOSFET performance. [D] . Nagavarapu, Venkatagirish. 2010

机译：平面源极袋（PSP）隧道MOSFET：适用于低功耗应用并改善隧道MOSFET性能的潜在器件解决方案。
6. High-performance III-V MOSFET with nano-stacked high-k gate dielectric and 3D fin-shaped structure [O] . Szu-Hung Chen, Wen-Shiang Liao, Hsin-Chia Yang, 2012

机译：具有纳米堆叠的高k栅极电介质和3D鳍形结构的高性能III-V MOSFET
7. A SiGe-Source Doping-Less Double-Gate Tunnel FET: Design and Analysis Based on Charge Plasma Technique with Enhanced Performance [O] . Varun Mishra, Yogesh Kumar Verma, Santosh Kumar Gupta, 2021

机译：一种SiGe源掺杂的双栅极隧道FET：基于增强性能的充电等离子体技术的设计与分析

A simulation study of the influence of a high-k insulator and source stack on the performance of a double-gate tunnel FET

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