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Parallel implementation of pulse compression method on a multi-core digital signal processor

机译：多核数字信号处理器脉冲压缩方法的平行实现

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Abdessamad Klilou; Assia Arsalane;
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年度 2020
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1. Parallel implementation of pulse compression method on a multi-core digital signal processor [J] . Abdessamad Klilou, Assia Arsalane International Journal of Electrical and Computer Engineering . 2020,第6期

机译：多核数字信号处理器脉冲压缩方法的平行实现
2. Real-time parallel implementation of Pulse-Doppler radar signal processing chain on a massively parallel machine based on multi-core DSP and Serial RapidIO interconnect [J] . Abdessamad Klilou, Said Belkouch, Philippe Elleaume, EURASIP journal on advances in signal processing . 2014,第1期

机译：基于多核DSP和串行RapidIO互连的大规模并行机上脉冲多普勒雷达信号处理链的实时并行实现
3. An efficient and scalable parallel mapping of pulse-Doppler radar signal processing chain on a multi-core DSP [J] . Klilou Abdessamad, Arsalane Assia, Najoui Mohamed, Microprocessors and microsystems . 2021,第Sepa期

机译：多核DSP上脉冲多普勒雷达信号处理链的高效且可伸缩的并行映射
4. Parallelization method of digital signal processing based on multi-core pipeline [C] . Shuai Weiyi, Yan Di, Li Xiaoyu, IEEE International Conference on Communication Technology . 2017

机译：基于多核流水线的数字信号处理并行化方法
5. Theory and implementation of pulse width modulation speed control of brushless DC motor using digital signal processor. [D] . Cheung, Hugo Chong-hing. 1992

机译：基于数字信号处理器的无刷直流电动机脉宽调制速度控制的理论与实现。
6. A Parallel Architecture for the Partitioning around Medoids (PAM) Algorithm for Scalable Multi-Core Processor Implementation with Applications in Healthcare [O] . Hassan Mushtaq, Sajid Gul Khawaja, Muhammad Usman Akram, 2018

机译：围绕Medoids（PAM）算法进行分区的并行体系结构可实现可扩展的多核处理器及其在医疗保健中的应用
7. Real-time parallel implementation of Pulse-Doppler radar signal processing chain on a massively parallel machine based on multi-core DSP and Serial RapidIO interconnect [O] . 2014

机译：基于多核DSP和串行RapidIO互连的大规模并行机上脉冲多普勒雷达信号处理链的实时并行实现
8. FPGA-Based Filterbank Implementation for Parallel Digital Signal Processing [R] . Berner, Stephan, DeLeon, Phillip 1999

机译：基于FpGa的并行数字信号处理滤波器组实现

Parallel implementation of pulse compression method on a multi-core digital signal processor

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