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A Power-Efficient 3-D On-Chip Interconnect for Multi-Core Accelerators with Stacked L2 Cache

机译：具有堆叠L2缓存的多核加速器的功率高效的3-D片上互连

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Kyungsu Kang; Sangho Park; Jong-Bae Lee; Luca Benini; Giovanni De Micheli;
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年度 2016
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1. Architecting On-Chip Interconnects for Stacked 3D STT-RAM Caches in CMPs [J] . Asit K. Mishra, Xiangyu Dong, Guangyu Sun, Computer architecture news . 2011,第3期

机译：为CMP中的堆叠3D STT-RAM缓存设计片上互连
2. Cost-Effective Design of Mesh-of-Tree Interconnect for Multicore Clusters With 3-D Stacked L2 Scratchpad Memory [J] . Kang Kyungsu, Benini Luca, De Micheli Giovanni Very Large Scale Integration (VLSI) Systems, IEEE Transactions on . 2015,第9期

机译：具有3-D堆栈式L2 Scratchpad内存的多核集群的树状网格互连的经济高效设计
3. Performance/Thermal-Aware Design of 3D-Stacked L2 Caches for CMPs [J] . GUANGYU SUN, HUAZHONG YANG, YUAN XIE ACM Transactions on Design Automation of Electronic Systems . 2012,第2期

机译：用于CMP的3D堆栈L2缓存的性能/热感知设计
4. A power-efficient 3-D on-chip interconnect for multi-core accelerators with stacked L2 cache [C] . Kyungsu Kang, Sangho Park, Jong-Bae Lee, Design, Automation Test in Europe Conference Exhibition . 2016

机译：具有堆叠L2高速缓存的多核加速器的节能3D片上互连
5. Serial Code Accelerators for Heterogeneous Multi-core Processor with Three-Dimensional Stacked Memory. [D] . Jacob, Philip. 2010

机译：具有三维堆栈存储器的异构多核处理器的串行代码加速器。
6. Development of a Non-Invasive On-Chip Interconnect Health Sensing Method Based on Bit Error Rates [O] . Insun Shin, Kyoungmin Koo, Daeil Kwon 2018

机译：基于误码率的非侵入式片上互连健康感测方法的开发
7. Cost-Effective Design of Mesh-of-Tree Interconnect for Multicore Clusters With 3-D Stacked L2 Scratchpad Memory [O] . Kyungsu Kang, Luca Benini, Giovanni De Micheli 2015

机译：具有3-D堆叠L2 Scratchpad内存的多核群集的树木树木互连的成本效益设计
8. Scalable System Architecture for Use With Free Space Optical Interconnects in a 3-D Stacked Processor Environment [R] . Rorie, J. J. 1999

机译：可扩展的系统架构，用于3-D堆叠处理器环境中的自由空间光互连

A Power-Efficient 3-D On-Chip Interconnect for Multi-Core Accelerators with Stacked L2 Cache

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