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Simultaneous Multi-Topology Multi-Objective Sizing Across Thousands of Analog Circuit Topologies

机译：同时多拓扑多目标尺寸跨数千个模拟电路拓扑

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Trent McConaghy; Pieter Palmers; Georges Gielen; Michiel Steyaert;
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年度 2007
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1. Synthesis of topology and sizing of analog electrical circuits by means of genetic programming [J] . J.R. Koza, F.H Bennett III, D. Andre Computer Methods in Applied Mechanics and Engineering . 2000,第2a4期

机译：遗传编程合成拓扑并确定模拟电路的大小
2. Simultaneous topology, shape, and size optimization of trusses, taking account of uncertainties using multi-objective evolutionary algorithms [J] . Techasen Teerapol, Wansasueb Kittinan, Panagant Natee, Engineering with Computers . 2019,第2期

机译：使用多目标进化算法同时考虑不确定性，同时进行桁架的拓扑，形状和尺寸优化
3. A novel self-adaptive hybrid multi-objective meta-heuristic for reliability design of trusses with simultaneous topology, shape and sizing optimisation design variables [J] . Panagant Natee, Bureerat Sujin, Tai Kang Structural and multidisciplinary optimization . 2019,第5期

机译：具有同声拓扑，形状和尺寸优化设计变量的桁架可靠性设计的新型自适应混合多目标元态
4. Simultaneous multi-topology multi-objective sizing across thousands of analog circuit topologies [C] . Trent McConaghy, Pieter Palmers, Georges Gielen, Annual conference on Design automation;Conference on Design automation . 2007

机译：跨数以千计的模拟电路拓扑结构同时进行多拓扑结构多目标调整
5. Algorithms for topology synthesis of analog circuits [D] . Das, Angan 2008

机译：模拟电路拓扑综合算法
6. Multi-Objective Topology Optimization of a Compliant Parallel Planar Mechanism under Combined Load Cases and Constraints [O] . Gao Wang, Dachang Zhu, Ning Liu, 2017

机译：组合工况和约束条件下柔性平行平面机构的多目标拓扑优化
7. Automatic Synthesis Using Genetic Programming of Both the Topology and Sizing for Five Post-2000 Patented Analog and Mixed Analog-Digital Circuits [O] . Matthew J. Streeter, Martin A. Keane, John R. Koza 2003

机译：使用2000年后获得专利的五个模拟和混合数字电路的拓扑和尺寸调整的遗传规划自动综合
8. ALGEBRAIC TOPOLOGY OF NETWORKS with application to POTENTIOMETER ANALOG CIRCUITS Part I: THEORY [R] . Lorenzo Calabi 1956

机译：应用于电位计模拟电路的网络代数拓扑结构第一部分：理论

Simultaneous Multi-Topology Multi-Objective Sizing Across Thousands of Analog Circuit Topologies

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