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>Built-in self-test technique for selective detection of neighbourhood pattern sensitive faults in memories
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Built-in self-test technique for selective detection of neighbourhood pattern sensitive faults in memories
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机译:内置自检技术,用于选择性检测存储器中的邻域模式敏感故障
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摘要
Traditional tests for memories are based on conventional fault models, involving the address decoder, individual memory cells and a limited coupling between them. The algorithms used in these tests have been successively augmented to consider stronger coupling conditions. Built-in self-test (BIST) solutions for testing memories today incorporate hardware for test pattern generation and application for a variety of these algorithms. This paper presents a BIST implementation for detection of neighbourhood pattern sensitive faults (NPSFs) in random access memories (RAMs). These faults are of different classes and types. More specifically, active, passive and static faults for distance 1 and 2 neighbourhoods, of types 1 and 2, are considered. It is shown how the proposed address generation and test pattern generation schemes can be made scaleable for the given fault type under consideration.
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