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An efficient hardware implementation of 64-bit block cipher algorithm HIGHT

机译：64位块密码算法高效硬件实现

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Hae-Won Park; Kyung-Wook Shin;
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年度 2011
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1. Efficient and high-throughput application-specific integrated circuit implementations of HIGHT and PRESENT block ciphers [J] . Bahram Rashidi Circuits, Devices & Systems, IET . 2019,第6期

机译：高效和高吞吐量的应用专用集成电路实现的高效和呈现块CIPHERS
2. High-throughput and lightweight hardware structures of HIGHT and PRESENT block ciphers [J] . Rashidi Bahram Microelectronics journal . 2019,第AUGa期

机译：HIGHT和PRESENT分组密码的高吞吐量和轻量级硬件结构
3. High-throughput and lightweight hardware structures of HIGHT and PRESENT block ciphers [J] . Rashidi Bahram Microelectronics journal . 2019,第Auga期

机译：高通量和轻质硬件结构的高吞吐量和目前的块密码
4. Design of Secured Block Ciphers PRESENT and HIGHT Algorithms and its FPGA Implementation [C] . R.S. Mahantesh, Sasmita Mohapatra International Conference on Intelligent Computing and Control Systems . 2018

机译：安全分组密码PRESENT和HIGHT算法的设计及其FPGA实现
5. New efficient block-based motion estimation algorithms for video compression and their hardware implementations. [D] . Rehan, Mohamed Mohamed. 2006

机译：用于视频压缩的新型高效的基于块的运动估计算法及其硬件实现。
6. Efficient Hardware Implementation of the Lightweight Block Encryption Algorithm LEA [O] . Donggeon Lee, Dong-Chan Kim, Daesung Kwon, 2014

机译：轻量级块加密算法LEA的高效硬件实现
7. An Efficient Hardware Implementation of ARIA Block Cipher Algorithm Supporting Four Modes of Operation and Three Master Key Lengths [O] . Dong-Hyeon Kim, Kyung-Wook Shin 2012

机译：ARIA块密码算法的高效硬件实现支持四种操作模式和三个主密钥长度

An efficient hardware implementation of 64-bit block cipher algorithm HIGHT

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