Evaluation of pausible clocking for interfacing high speed IP cores in GALS framework

摘要

Pausible clocking schemes have been proposed by GALS architects as a promising mechanism for reliable data transfer between synchronous modules fed by low-speed independent clocks. In this paper, we argue that existing schemes are not well-suited for interfacing high-speed IP cores with large clock-distribution tree delay and high communication rates. We propose an alternative interface circuit design for such IP cores that works with partial handshake between communicating modules and minimizes the performance penalty of the sender and receiver. Our circuit, unlike pausible clocking, has a small probability of failure.