Study of SILC and interface trap generation due to high field stressing and its operating temperature dependence in 2.2 nm gate dielectrics

摘要

Reports study of metal-oxide-semiconductor (MOS) capacitors with 2.2 nm dry and N2O grown gate dielectrics. Interface trap generation during constant voltage stressing at different operating temperatures (from 22°C to 90°C) has been investigated. The effect of nitrogen annealing (20 min) at 400°C on high temperature stress-induced interface traps was also studied.