Analyses of parasitic capacitance effects and flicker noise of the DAC capacitor array for high resolution SAR ADCs

摘要

With the increasing number of bits, parasitic effects and flicker noise of switching transistors in the DAC capacitor array of the SAR ADC are getting relatively bigger when compared to the exponentially decreasing error budget. This paper analyses the effects of parasitic capacitances related to the top-plate and bottom-plate of unit capacitors on the accuracy and the noise performance of the DAC capacitor array, showing that thermal noise of the whole capacitor array decreases when parasitic capacitances are considered while in the meantime an unexpected gain error is introduced. Although the parasitic-capacitance-induced gain error is almost independent of the number of bits, parasitic effects should be minimized for high resolution SAR ADCs since the dynamic range of the high resolution ADC is severely reduced due to the gain error. The post-layout parasitic capacitance extraction of a 10-bit poly-poly DAC capacitor array shows that the value difference between the top-plate and bottom-plate related parasitic capacitances is large so that the parasitic-capacitance-induced gain error can be decreased by 152 times when top-plates of unit capacitors are connected together as the output node of the capacitor array. The switching transistor’s flicker noise calculation for a 10-bit SAR ADC shows that flicker noise can be safely ignored for 10-bit 1MSPS SAR, while the calculation for an 18-bit 1MSPS SAR ADC shows that flicker noise should be considered for the higher resolution SAR ADCs.