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Verification Platform of 40Gbps High-speed Serial Interface Chip Based on UVM

机译：基于UVM的40Gbps高速串行接口芯片验证平台

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1. A Simple Modelling Tool for Fast Combined Simulation of Interconnections, Inter-Symbol Interference and Equalization in High-Speed Serial Interfaces for Chip-to-Chip Communications [J] . Davide Menin, Thomas Bernardi, Alessio Cortiula, Advances in Science, Technology and Engineering Systems . 2020,第2期

机译：用于芯片到芯片通信的高速串行接口中互连，符号间干扰和均衡的快速组合模拟简单建模工具
2. On Error Injection for NoC Platforms: A UVM-Based Generic Verification Environment [J] . El-Ashry Sameh, Khamis Mostafa, Ibrahim Hala, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems . 2020,第5期

机译：关于NOC平台的错误注射：基于UVM的通用验证环境
3. Implications of On-Chip Single-Source Clocking on High-Speed Serial Interfaces in Network SoC [J] . Maneesh Kumar Pandey, Tuhina Gupta, Pallavi Raj, Design & Test of Computers, IEEE . 2019,第4期

机译：片上单源时钟对网络SoC中高速串行接口的影响
4. Design and experimental verification of on-chip signal integrity analyzer (OSIA) scheme for eye diagram monitoring of a high-speed serial link [C] . Shin Minchul, Kim Myunghoi, Koo Kyoungchoul, 2011 IEEE International Symposium on Electromagnetic Compatibility . 2011

机译：用于高速串行链路眼图监视的片上信号完整性分析器（OSIA）方案的设计和实验验证
5. Single chip high-speed serial link communications for multi-channel and multi-standard applications [D] . Hsieh, Ming-ta 2008

机译：用于多通道和多标准应用的单芯片高速串行链路通信
6. Brain-Computer Interface application: auditory serial interface to control a two-class motor-imagery-based wheelchair [O] . Ricardo Ron-Angevin, Francisco Velasco-Álvarez, Álvaro Fernández-Rodríguez, 2017

机译：脑机接口应用程序：听觉串行接口可控制两类基于运动图像的轮椅
7. The High-speed Interface Design Based on PCIe of the Non-cooperative Receiver Verification Platform [O] . Li Xiao Ning, Yao Yuan Cheng, Qin Ming Wei 2017

机译：基于PCIE的非合作接收机验证平台的高速接口设计

Verification Platform of 40Gbps High-speed Serial Interface Chip Based on UVM

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