Hardware-Transactional-Memory Based Speculative Parallel Discrete Event Simulation of Very Fine Grain Models

摘要

This article presents an innovative runtime supportudfor speculative parallel processing of discrete event simulationudmodels on multi-core architectures, which exploitsudHardware-Transactional-Memory (HTM) facilities for the purposeudof state recoverability. In this proposal, the speculativeudupdates on the state of the simulation model are executed asudconcurrent HTM-based transactions that are also in charge ofuddetecting whether the update is consistent with the advancementudof logical-time along model execution. Our proposal isudfully transparent to the application code. Hence, our HTMbasedudrun-time support can host conventionally developeduddiscrete event models relying on the concept of event-handlersudto be dispatched by an underlying simulation engine. Experimentaluddata show that our proposal provides 75% to 92%udof the ideal speedup on an Intel Haswell based platformud(equipped with 4 physical cores and HTM support) for discreteudevent models with event granularity ranging between 2 andud12 microseconds. The data also show that these same modelsudcannot be executed efficiently on top of a last generationudparallel discrete event simulation platform employing software-basedudrecoverability