'Analogue Network of Converters': A DFT Technique to Test a Complete Set of ADCs and DACs Embedded in a Complex SiP or SOC

摘要

A new method has been developed to test a pool of ADCs and DACs embedded in a complex SiP or SoC. This method has been developed concidering current test constraints. Indeed due to system design trends, theses constraints are: a few number of access points to the primary inputs of the converters and the increase of the nnumber and the performances of the converters under test. In order to test these converters, we propose to connect them in the analog domain. As a consequence we need only digital test instruments to generate the test stimuli and capture the test responses. A signal processing routine has been developed in order to discriminate the errors from DACs and ADCs. The approac has been validated through simulations and experimentations. Finally I have extend the application domain of the method to the test of stand-alone ADCs and DACs.