On the robustness of R-2R ladder DACs

摘要

A model of the linear R-2R ladder digital-to-analog converter (DAC) is developed in terms of the ratios of the effective resistances at the nodes of the ladder. This formulation demonstrates clearly why an infinite number of different sets of resistors can produce the same linearity error and shows how this error can be reduced by trimming. The relationship between the weights of the bits and the resistor ratios suggests appropriate trimming, design, and test strategies