首页> 外文OA文献 >Enhancement of timing accuracy and waveform quality in high performance ASIC test and verification systems.
【2h】

Enhancement of timing accuracy and waveform quality in high performance ASIC test and verification systems.

机译:高性能ASIC测试和验证系统中定时精度和波形质量的增强。

摘要

This thesis reviews design, test, and verification aspects of Application-Specific Integrated Circuits (ASIC). A means of improving edge-placement accuracy and waveform quality in high speed, high performance, ASIC test and verification systems has been developed. Its aim is to minimize timing skew, maintain signal integrity at the Device Under Test (DUT), and actively reduce waveform distortions caused by uncertain DUT loading and transmission path imperfections. Frequency Domain Reflectometry (FDR) is used to measure voltage reflection coefficients of both the load (DUT) and Pin Electronic Card (PEC) ends of the transmission path. Time domain waveform is obtained using Discrete Fourier Transformation (DFT). Two prototypes, single and dual directional couplers, have been designed and implemented using Thickfilm-Hybrid Technology (TFH). Both couplers employ strip transmission line structures which support a Transverse Electromagnetic (TEM) propagation mode. FDR experimental results indicate that a matched dual direction.al coupler can be used in such an application, yielding results comparable to those obtained from an automatic network analyzer. The path between the PEC and the DUT is modelled using a signal flow graph (SFG) technique. The model contains both lumped, and distributed circuit elements, each of which is represented by scattering parameters. Load models that represent the DUT or PEC receiver are obtained through a direct search optimization algorithm. This thesis implements two such algorithms, the pattern search and simplex algorithms, based on an example load model. A technique to compute compensation waveforms for linear transmission paths has been developed. Two examples, matched and mismatched channels, are presented. Simulation results show that compensation waveforms computed from the channel characteristic almost completely correct edge-placement timing errors and greatly reduce reflection effects. Implementation of compensation waveforms by simple hardware is possible, leading to edge-placement correction which is almost as good as that obtained from a theoretically computed compensation waveform.
机译:本文回顾了专用集成电路(ASIC)的设计,测试和验证方面。已经开发出一种在高速,高性能,ASIC测试和验证系统中提高边缘放置精度和波形质量的方法。其目的是最大程度地减少时序偏斜,保持被测设备(DUT)的信号完整性,并积极减少由于不确定的DUT负载和传输路径缺陷而导致的波形失真。频域反射法(FDR)用于测量传输路径的负载(DUT)和针式电子卡(PEC)两端的电压反射系数。使用离散傅里叶变换(DFT)获得时域波形。已使用厚膜混合技术(TFH)设计和实现了两个原型,即单向和双向定向耦合器。两个耦合器均采用支持横向电磁(TEM)传播模式的带状传输线结构。 FDR实验结果表明,可以在此类应用中使用匹配的双向定向耦合器,其结果可与从自动网络分析仪获得的结果相媲美。 PEC和DUT之间的路径使用信号流图(SFG)技术建模。该模型既包含集总电路元素又包含分布式电路元素,每个元素均由散射参数表示。代表DUT或PEC接收机的负载模型是通过直接搜索优化算法获得的。本文基于示例负载模型,实现了两种这样的算法:模式搜索和单纯形算法。已经开发了一种计算线性传输路径的补偿波形的技术。给出了两个示例,匹配和不匹配的通道。仿真结果表明,由通道特性计算出的补偿波形几乎可以完全纠正边缘放置时序误差,并大大降低反射效应。可以通过简单的硬件实现补偿波形,从而导致边缘位置校正,该校正几乎与从理论上计算出的补偿波形获得的效果一样好。

著录项

  • 作者

    Charoen Boonying;

  • 作者单位
  • 年度 1991
  • 总页数
  • 原文格式 PDF
  • 正文语种 en
  • 中图分类

相似文献

  • 外文文献
  • 中文文献
  • 专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号