FPGA Implementation of a Real Time Maximum Likelihood Space-Time Decoder on a MIMO Software Radio Test Platform

摘要

This paper describes the concept, architecture,development and demonstration of a real time, maximumlikelihood Alamouti decoder for a wireless 4-transmit 4-receiver multiple input and multiple output (MIMO) Smart Antenna Software Radio Test System (SASRATS) platform. It is implemented on a Xilinx Virtex 2 Pro Field Programmable GateArray (FPGA). Hardware, firmware, use of the Xilinx CoreGenerator Intellectual Property modules and experimentalverification of the decoder are discussed.