Digitally enhanced CMOS RF transmitter with integrated power amplifier

摘要

An energy-efficient, 3.5 GHz, direct-conversion RF transmitter with integrated 23 dBm, Class-B power amplifier (PA) is fabricated in a 0.13 μm CMOS process. The TX chip is packaged using a low-cost chip-on-board (COB) technique. When 20-MHz bandwidth OFDM signals are transmitted, a high TX average power efficiency is achieved exploiting the dynamic current biasing of the Class-B PA and a low-loss output matching network using high-Q bondwire inductances in the package. Assisted by an integrated feedback path, a two-dimensional, digital look-up table (2-D LUT) adapted by complex gradient-descent algorithms compensates the I/Q mismatch and memoryless nonlinearities of the whole transmit path, including the severe amplitude and phase distortions of the on-chip PA. Fifth-order Butterworth transmit filters with 34 MHz cutoff frequency sufficiently attenuate the aliases of the 80 MS/s digital-to-analog converters (DACs), while retaining high in-band fidelity without corrupting the predistorted signal. When a 20 MHz, 64-QAM OFDM signal with 9.6 dB peak-to-average power ratio (PAPR) was transmitted, the measured average drain efficiency (DE) of the PA was 12.5% at 9.6 dB back-off and 17.5% at 7 dB back-off, and the corresponding error-vector magnitude (EVM) was measured −29.6 dB and −26.3 dB with equalization, respectively. Peak DE of 55% and 25 dBm saturated output power were also measured for the same PA in a stand-alone package.