Full chip modeling for predictive simulation of charged device model electrostatic discharge events

摘要

With downscaling of device dimensions in integrated circuits (ICs), the risk of circuit failure due to electrostatic discharge (ESD) is increasing. In particular, the increased usage of automated handlers is causing charged device model (CDM) ESD induced failures to become more prominent. Gate oxide failure is the primary signature of CDM ESD. During CDM, the IC is the source as well as the path for the static charge. Therefore, it is important to include the circuit elements representing the package, ESD circuits and the silicon substrate of the packaged ICs. Power domain crossing circuits, also known as internal I/Os, are susceptible to gate oxide damage during CDM events. In this thesis, circuit-level simulations of internal I/O circuits are used to elucidate the roles of the package, power clamp placement, anti-parallel diode placement and decoupling capacitors in determining the amount of stress at the internal I/O circuits. This thesis will also provide design recommendations for preventing CDM failures in the internal I/O circuits.