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Integrating wrapper design, TAM assignment, and test scheduling for SOC test optimization
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机译:集成包装器设计,TAM分配和测试计划以进行SOC测试优化
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摘要
Test time minimization for core-based designs is tightly integrated with wrapper design and TAM capacity. This paper presents a method to determine minimum SOC test schedules with wrapper design and TAM optimization based on simulated annealing. The method can handle SOC test scheduling with and without power constraints in addition to precedence constraints that preserve desirable orderings among tests. We present experimental results using the ITC 2002 benchmarks.
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