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Full-Custom Sub-/Near-Threshold Cell Library in 130nm CMOS with Application to an ALU

机译:130nm CMOS中的全定制子/近阈值单元库及其在ALU中的应用

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摘要

This thesis presents a cell library with limited functionality targeting to operate in sub-threshold (350mV) as well as above-threshold (1.2V) voltages utilizing the dynamic speed requirement of the circuit. The sub-threshold cell library can be used to synthesize any general Finite State Machine (FSM) since it contains logic gates and a D-FF memory element. The sub-threshold cell library proposed in this thesis consists of: Inverter, NAND2, NOR2, XNOR2, XOR2, AOI22, OAI22 and D flip-flop. All cells are designed with static CMOS and use of 130 nm HVT n-well process. The main motivation behind this work is the desirable for longer lasting battery powered IC chips. CMOS power consumption includes three components where the dynamic component is proportional to VDD^2. Hence, a promising method to reduce power consumption is to reduce the supply voltage to the sub-threshold region. The reduction of VDD increases the delay through the circuit (excellent trade-off in application with low performance requirements) and increases sensitivity to process, voltage and temperature (PVT) variations.The sub-threshold cells are evaluated with an ALU synthesized into three circuits: No.1: unlimited, with use of provided above-threshold cells; No.2: limited to INV, NAND2, NOR2 and D-FF with sub- and above-threshold cell library; and No.3: limited as No.2 + XNOR2, XOR2, AOI22 and OAI22 with sub- and above-threshold cell library.The results shows a power consumption reduction of ~14 times from VDD=1.2V to 350mV for both No.2 and No.3 ALU circuit. It is also shown that a more complex library including XNOR2, XOR2, AOI22 and OAI22 reduces the power consumption with ~7.7% compared to a library with only Inverter, NAND2, NOR2 and D-FF at 350mV. The No.3 circuit is shown to be the best ALU with use of sub-threshold cells in term of delay and power consumption. Both No.2 and No.3 only fails to comply with the 32KHz frequency in SS and FS corner within -40°C and 350mV with use of sub-threshold cells, whereas with above-threshold cells fails in all except FF corner in -40°C, in addition to failing in SS corner at 25°C.
机译:本文提出了一种功能有限的单元库,旨在利用电路的动态速度要求在低于阈值(350mV)和高于阈值(1.2V)的电压下工作。由于亚阈值单元库包含逻辑门和D-FF存储元件,因此它可用于合成任何通用的有限状态机(FSM)。本文提出的亚阈值单元库包括:反相器,NAND2,NOR2,XNOR2,XOR2,AOI22,OAI22和D触发器。所有单元均采用静态CMOS设计,并使用130 nm HVT n阱工艺。这项工作背后的主要动机是希望使用更持久的电池供电IC芯片。 CMOS功耗包括三个分量,其中动态分量与VDD ^ 2成比例。因此,降低功耗的一种有前途的方法是降低到亚阈值区域的电源电压。 VDD的降低会增加电路的延迟(在对性能要求较低的应用中进行出色的折衷),并增加了对工艺,电压和温度(PVT)变化的敏感性。亚阈值单元通过合成为三个电路的ALU进行评估:No.1:无限制,使用提供的阈值以上单元; No.2:仅限于具有低于阈值和高于阈值的单元库的INV,NAND2,NOR2和D-FF; No.3和No.3:限制为No.2 + XNOR2,XOR2,AOI22和OAI22,具有低于阈值和高于阈值的单元库,结果表明,这两种No.的功耗从VDD = 1.2V降低到350mV约14倍。 2和3号ALU电路。还显示出,与只有350mV的Inverter,NAND2,NOR2和D-FF的库相比,包括XNOR2,XOR2,AOI22和OAI22的更复杂的库将功耗降低了约7.7%。在延迟和功耗方面,使用亚阈值单元显示出No.3电路是最好的ALU。使用亚阈值单元,第2号和第3号都无法满足-40°C和350mV范围内SS和FS拐角处的32KHz频率,而具有高于阈值的单元在除-中的FF拐角以外的所有情况下均不合格- 40°C,除了25°C时SS角失败。

著录项

  • 作者

    Johnsen Glenn André;

  • 作者单位
  • 年度 2014
  • 总页数
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类

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