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Compensation of Threshold Voltage for Process and Temperature Variations in 28nm UTBB FDSOI

机译:针对28nm UTBB FDSOI中的工艺和温度变化的阈值电压补偿

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摘要

As technology scales down in order to meet demands of more computing power per area, a variety of challenges emerge. Devices with channel lengths of a few nano meters require atomic precision when they are manufactured. Small irregularities in the equipment and manufacturing environment can cause large process variations from die--to--die, but also within--die variations. Along with the increasing density of transistors per die which has led to severe performance issues due to temperature variations, these effects may seriously impact operation and cause large deviations in frequency and power across a the chip.This thesis will present the analysis and design of a circuit with the goal of compensating the threshold voltage, by means of body biasing, in order to mitigate process and temperature variations. The compensation circuit is designed to provide adaptive body biasing for a large number of equally matched devices within the chip, which may be useful in digital systems with many repetitive instances. Its functionality and effect will be tested by designing it to be used with a 13--stage inverter based ring oscillator operating at 65.5MHz, and observing the improvement in frequency variation across processing corners and a temperature range from -40 degrees Celsius to 80 degrees Celsius. All circuits were designed using a commercially available 28nm fdsoi transistor technology because of its excellent susceptibility to body biasing, and its promise as a competitive technology to continue Moore`s law.Results obtained by post--layout simulations on the ring oscillator show that frequency variations across processing corners and temperature has been reduced from 18.69% down to 0.632% by utilising adaptive body biasing provided by the compensation circuit. Ring oscillator frequency temperature sensitivity in a range from -40 degrees Celsius to 80 degrees Celsius for the typical corner is shown to be as little as 29.4ppm per degree Celsius
机译:随着技术的发展以适应每个区域更大的计算能力的需求,出现了各种各样的挑战。具有几纳米沟道长度的设备在制造时需要原子精度。设备和制造环境中的微小不规则性可能导致不同模具之间以及不同模具内部的工艺差异较大。随着每个管芯晶体管密度的增加(由于温度变化而导致严重的性能问题),这些影响可能会严重影响操作,并导致整个芯片的频率和功率发生较大偏差。该电路的目的是通过体偏置来补偿阈值电压,以减轻工艺和温度变化。补偿电路设计用于为芯片内的大量相等匹配的设备提供自适应主体偏置,这在具有许多重复实例的数字系统中可能很有用。将其设计为与工作于65.5MHz的基于13级反相器的环形振荡器一起使用时,将对其功能和效果进行测试,并观察跨处理角点和-40摄氏度至80摄氏度的温度范围内频率变化的改善情况摄氏温度所有电路均采用市售的28nm fdsoi晶体管技术进行设计,这是因为其对人体偏置的敏感性极强,并且有望成为延续摩尔定律的竞争技术。通过环形振荡器的布局后仿真获得的结果表明该频率通过利用补偿电路提供的自适应主体偏置,处理角和温度之间的变化从18.69%降低到0.632%。对于典型的转角,环形振荡器的频率温度灵敏度范围为-40摄氏度至80摄氏度,显示为每摄氏度低至29.4ppm

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    Strandvik Erlend;

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  • 年度 2015
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  • 原文格式 PDF
  • 正文语种 eng
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