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Techniques for automatic on chip closed loop transfer function monitoring for embedded charge pump phase locked loops.

机译:用于嵌入式电荷泵锁相环的自动片上闭环传递函数监视技术。

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摘要

Charge Pump Phase locked loops are used in a variety of applications, including on chip clock synthesis, symbol timing recovery for serial data streams, and generation of frequency agile high frequency carrier signals. In many applications PLLs are embedded into larger digital systems, in consequence, analogue test access is often limited. Test motivation is thus towards methods that can either aid digital only test of the PLL, or alternatively facilitate complete self testing of the PLL. One useful characterisation technique used by PLL designers is that of closed loop phase transfer function measurement. This test allows, an estimation of the PLL's natural frequency, damping, and 3 dB bandwidth to be made from the magnitude and phase response plots. These parameters relate directly to the time domain response of the PLL and will indicate errors in the PLL circuitry. This paper provides suggestions towards test methods that use a novel maximum frequency detection technique to aid automatic measurement of the closed loop phase transfer function. In addition, techniques presented have potential for full BIST applications.
机译:电荷泵锁相环用于各种应用中,包括片上时钟合成,串行数据流的符号定时恢复以及频率捷变的高频载波信号的生成。在许多应用中,PLL被嵌入到较大的数字系统中,因此,模拟测试访问通常受到限制。因此,测试动机是针对可以辅助PLL的仅数字测试,或者可以促进PLL的完全自测试的方法。 PLL设计人员使用的一种有用的表征技术是闭环相转移函数测量。该测试允许根据幅度和相位响应图来估算PLL的固有频率,阻尼和3 dB带宽。这些参数直接与PLL的时域响应有关,并将指示PLL电路中的错误。本文针对使用新颖的最大频率检测技术来辅助闭环相位传递函数的自动测量的测试方法提供了建议。另外,提出的技术有可能用于完整的BIST应用。

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