Implementation of Maximum Likelihood Decoding for Trellis Codes and Trellis Coded Modulation

摘要

A single chip implementation of a maximum likelihood decoder for use with convolutional codes and trellis coded modulation is described. After a detailed study of various configurations for the chip, a much improved architecture was arrived at. Central to this architecture is a canonical rate 1/2,64 state code which has become the defacto standard for the industry. As before, higher rate codes are obtained by puncturing the code. What is novel in this new architecture is that the encoder and decoder for this one code are used as the encoder and decoder for trellis coded modulation for 8-PSK, 16-PSK, and various QAM signal constellations. The result was the design of a single chip implementation of a maximum likelihood decoder for use with both convolutional codes and trellis coded modulation.