MOSFET Level 1 and 2 Models in APLAC

摘要

The report documents the APLAC implementations of SPICE level 1 and 2 MOS models.First a set of mappings is derived for handling NMOS and PMOS transistors in all operating regions based on the equations of an NMOS transistor with V(ds) = or > 0. Then the model equations of the NMOS transistor are presented. Two drain current models are covered. These are SPICE level 1 and SPICE level 2. The documentation consists of all the equations required for the implementation including the substrate diode models, temperature dependencies and noise equations. The intrinsic charge models presented are the simplified Yang-Chatterjee model and the Ward-Dutton model. Also the extrinsic capacitance model is documented.