Manufacturing Methods and Technology Project to Establish and Improve the Producibility of Silk Screening and Layering of Ceramic Dielectric Capacitors.

摘要

A summary manufacturing methods and technology engineering for silk screening and layering three dielectric capacitor types is presented. Chip capacitors to be manufactured using .0005inch dielectric rated at 50volts at a pro-dunction rate of 5000units per day. Internal electrodes shall be of a basemetal or alloy that will provide for an objective of 80% cost reduction from the use of palladuim. End terminations shall be of the same material and must be capable of immersion for seconds at 500F in 60/40solder.