A MULTIPROCESSOR COMPUTER SIMULATION MODEL EMPLOYING A FEEDBACK SCHEDULER/ALLOCATOR FOR MEMORY SPACE AND TMR PROCESSING

摘要

A computer simulation model for a multiprocessor computer is devel¬oped that is useful for studying the problem of matching a multiprocessor's memory space, memory bandwidth and numbers and speeds of processors with aggregate job set characteristics. The model assumes an input work load x of a set of recurrent jobs. A minimal amount of knowledge of individual job requirements for bandwidth is assumed. The model includes a feed¬back scheduler/allocator which attempts to improve system performance through higher memory bandwidth utilization by matching individua1 job requirements for space and bandwidth with space availability and esti¬mates of bandwidth availability at the times of memory allocation. This matching factor is then fed back into the job scheduler via internal job priority. A nonfeedback version is made available for comparison purposes and an independent analysis is made to determine maximum improvements. The simulation model includes provisions for specifying precedencenrelations among the jobs in a job set. Provisions for specifying precedence execution of TMR (Triple Modular Redundant and SIMPLEX (Non Redundant) jobs. Some typical problems are studied by means of the simulator.