A SIMULATION ANALYSIS OF PHASE PROCESSING CIRCUITRY IN THE OHIO UNIVERSITY OMEGA RECEIVER PROTOTYPE

摘要

The goals of the simulation were fourfold:nA. To analyze the circuits on a bit-by-bit level in order to evaluate the overall design;nB. To see easily the effects of proposed design changes prior to actual breadboarding;nC. To determine the optimum integration time for the DPLL in an environ-ment typical of general aviation conditions;andnD. To quantify the phase error introduced by the SRM synthesizer and examine its effect on the system.