Controlled Impedance Short Circuit Limiter. Research Report 654

摘要

Fault currents in power systems are increasing and are approaching the rating limits of installed equipment, particularly circuit breakers. Various approaches for limiting fault currents have been proposed, and this program was directed to investigating a specific approach: the Controlled Impedance Short Circuit Limiter (CISCL). The CISCL places in each line a series tuned inductor-capacitor circuit having virtually zero impedance during normal operation but is rapidly switched to a parallel tuned, high resistive impedance at the start of a fault, limiting the current before the first high current peak. The CICSL and several of its variations were analyzed by digital computer simulation and scaled-down model testing. Performance and economic factors were evaluated, and optimum design guidelines were established for an assumed system of rated 300 MVA at 145 kV; however, the results are applicable for a wide range of ratings. With CISCL the fault current has relatively little offset, the instantaneous peak let-thru current can be held at 2 times rated current or lower and is also resistive. The losses are typically 0.1 percent of the through-put power. Costs of components vary from $1500 to $3900 per MVA (based on 1976 costs) depending on the particular performance desired. Following the study of the technical and economic factors associated with the CISCL, a specific application was selected to serve as a basis for a prototype design. The selected application was on the Consolidated Edison Company system and involved incorporating the CISCL in a bus tie location at its Farragut substation. The prototype was designed for a rating of 345 kV and 2000 amperes and limited the peak let-thru current to 16.5 kA and the steady-state fault current to 4250 A. The estimated cost of the prototype is $5,000,000. (ERA citation 04:026269)