Vertical Charge Transport in Junction Charge-Coupled Devices

摘要

Vertical charge transport in junction charge coupled devices (JCCD's) and its application in logic circuits were analyzed. Charge can be vertically injected into the JCCD transport channel through the steering gates by applying a vertical NPN transistor (injector), which can be made without any additional fabrication processing steps. The substrate PNP transistor, formed by the steering gate, the transport channel, and the substrate, can be used for the detection of surplus charge. The substrate PNP transistor was applied in a very simple, amplifying JCCD output structure, having a gain more than 100 while harmonic distortion is less than - 50 dB. Circuits based on vertical charge injection and vertical charge overflow of surplus charge were realized. And-or-invert circuits were operated at more than 50 MHz. A Full Adder was operated at 5 MHz. Performance can be improved by a fast charge-normalizing stage and a thinner epilayer.