Performance of Front-End Readout System for PHENIX RICH

摘要

A front-end electronics system has been developed for the Ring Imaging Cherenkov211u001e(RICH) detector of the PHENIX experiment at the Relativistic Heavy Ion Collider 211u001e(RHIC), Brookhaven National Laboratory (BNL). A high speed custom back-plane with 211u001esource synchronous bus architecture, a full custom analog ASIC, and board modules 211u001ewith FPGA's and CPLD's were developed for high performance real time data 211u001eacquisition. The transfer rate of the back-lane has reached 640 MB/s with 128 211u001ebits data bus. Total transaction time is estimated to be less than 30 (micro)s 211u001eper event. The design specifications and test results of the system are presented 211u001ein this paper.