New technique for imaging the logic state of passivated conductors: Biased resistive contrast imaging.

摘要

A new scanning electron microscopy imaging technique has been developed to examine the logic state of conductors on passivated CMOS integrated circuits. This technique employs a modified Resistive Contrast Imaging system to acquire image data on powered devices. The image is generated by monitoring subtle shifts in the power supply current of an integrated circuit as an electron beam is scanned over the device surface. The images produced with this new technique resemble voltage contrast data from devices with the passivation removed and the surface topography subtracted. Non-destructive applications of this imaging method to functional and failed integrated circuits are described. Possible irradiation effects and methods to minimize them are also discussed. 2 refs., 1 fig.