Ultra - Low - Power Asynchronous Processor and FPGA Design using Straintronics Nanomagnets.

摘要

This seed and exploratory grant was funded to generate some initial results that are presented in this report. The project was funded by Dr. Robert Coswell in Nov. 2010 in consultation with Dr. Devanand Shenoy to develop a fusion of strain-based spintronics, as well as spin torque transfer devices, and CMOS VLSI technologies. The project was initiated with the hope to start extensive work in non-volatile and ultra-low-power subthreshold and superthreshold VLSI circuits relevant for a wide spectrum of military and space electronic systems. In this project we demonstrated: (1) an ultra-low power hearing aid speech processor interfacing with a custom designed SRAM to operate fully in sub-threshold regime (Specs: Operating at 1MHz clock frequency; 600 pJ consumption for each FIR operation); (2) a 128 point FFT/IFFT processor in 65nm technology operating in subthreshold regime (Specs: Operates at 1 MHz; energy consumption of 31 nJ/FFT); (3) a sub-threshold operating asynchronous 8051 microcontroller (A8051) with a novel 16T SRAM cell for improved performance and reliability (Specs: Consumes 91.6 nW at 250 mV. New 16T SRAM block consumes 5.44 pJ for writing and 9.08 pJ for reading); and (4) a 2 KB nonvolatile straintronics memory with 1.3 pJ read power. A follow-up grant is, therefore, requested to support three graduate students who have enthusiastically worked on this project for one year and are now poised to conduct more creative investigations in this promising emerging technology.