Finite Element Modeling and Analysis of MCM High Density Interconnect Vias

摘要

Failure modes of vias within a chip's first multi-chip module are studied usingseveral two and three-dimensional families of finite element models. The models study both the global strains of the entire module and local strains of a single via under uniform temperature loading between -65 deg C and 120 deg C. The accuracy of the models was verified by comparing different families of models with each other, with analytical beam theory, and with empirical data generated by electron beam moire strain data taken by NIST on a test specimen. Global finite element analysis results revealed that the strains within the high density interconnect layer have only a 10% effect upon the local via strains. A simple analytical method was developed to obtain displacement boundary conditions to be applied to local via finite element models, thereby precluding the need for global finite element analysis of the entire module. For a local via analysis, the axisymmetric and three-dimensional finite element models were found to predict the location of via failures, which agrees with failure locations observed under accelerated test conditions. A number of via design factors were identified that affect the strain concentration in the via wall. However, the dielectric/epoxy intermaterial boundary was not found to be the cause of the strain concentration in the via wall.