Self-Synchronous Schemotechnique as a Design Basis for The Fail-Safe Wafer ScaleIntegration Emergency Computers. Report Number 2

摘要

This report results from a contract tasking Institute of Informatics Problems(IPI RAN) as follows: The contractor will prepare a detailed technical report to include the analysis of present state trends in the development of computer systems IC base including a description of requirements for Emergency Computer schemotechnique. This report will also include a discussion of the main principles of self-timing as well as analysis and description.