Chip to System Testability

摘要

The ultimate objective of the Chip-to-System Testability program was thedevelopment of a structured testability implementation methodology which will be used as a basis for a PC-based tool called TESPAD. This tool can be used by development contractors and program offices to establish testability requirements that are verifiable and cost effective for implementation in electronic systems. Given a set of functional system design requirements, the type of system to be procured (i.e., airborne, ground-based etc.) and some information about the types of circuits involved in the different levels of the system hierarchy, TESPAD makes use of this structured testability methodology by defining and allocating detailed testability design and validation requirements including testability measures, recommended DFT/BIT methods and structures, data formats and data delivery, and validation and verification procedures. To accomplish this goal, it was necessary to complete a number of predecessor tasks including: (1) Evaluation of positive and negative impacts of testability applied at all levels of the design hierarchy of electronic systems, and (2) Identify chip through system level test performance that can be achieved (as measured by common testability figures of merit) using current test technology for various types of design technology.